Transaction

jmetaB03db3a9a6fa2efa6ace87b2f1865b1778a08f92f8bb0d32b84596ddc45fa6f8aff@104e04f4dc7bbb58b675a0be8ec8a2392cd828cadc0c1b85347e2d4ab003150erss.itemmetarss.netM:<item> <title>Hardware-based stack buffer overflow attack detection on RISC-V architectures</title> <link>https://arxiv.org/abs/2406.10282</link> <description>arXiv:2406.10282v1 Announce Type: new Abstract: This work evaluates how well hardware-based approaches detect stack buffer overflow (SBO) attacks in RISC-V systems. We conducted simulations on the PULP platform and examined micro-architecture events using semi-supervised anomaly detection techniques. The findings showed the challenge of detection performance. Thus, a potential solution combines software and hardware-based detectors concurrently, with hardware as the primary defense. The hardware-based approaches present compelling benefits that could enhance RISC-V-based architectures.</description> <guid isPermaLink="false">oai:arXiv.org:2406.10282v1</guid> <category>cs.CR</category> <arxiv:announce_type>new</arxiv:announce_type> <dc:rights>http://creativecommons.org/licenses/by-nc-sa/4.0/</dc:rights> <dc:creator>Cristiano Pegoraro Chenet, Ziteng Zhang, Alessandro Savino, Stefano Di Carlo</dc:creator> </item>