Transaction

c4c173f62c5a7142d35c783722873a96b5ce8350bf0ba93356917b75bfd35a96
Timestamp (utc)
2024-03-24 01:27:27
Fee Paid
0.00000012 BSV
(
0.02068555 BSV
-
0.02068543 BSV
)
Fee Rate
10.32 sat/KB
Version
1
Confirmations
86,389
Size Stats
1,162 B

2 Outputs

Total Output:
0.02068543 BSV
  • j"1LAnZuoQdcKCkpDBKQMCgziGMoPC4VQUckM<div class="post"><div class="quoteheader"><a href="https://bitcointalk.org/index.php?topic=941.msg11492#msg11492">Quote from: tcatm on August 28, 2010, 10:12:18 AM</a></div><div class="quote"><div class="quoteheader"><a href="https://bitcointalk.org/index.php?topic=941.msg11484#msg11484">Quote from: BioMike on August 28, 2010, 08:24:05 AM</a></div><div class="quote">So, what CPU's support this? Is this only the newest AMD ones? And how many systems are we excluding because of this?<br/></div><br/>Phenoms, i5 and i7 from what I know. Those are the only CPUs that have a 128 bit SSE2 instruction decoder and benefit at all, every older CPU will be slower. Don't think about it as "only works on AMDs K10" but rather as "tweak the compiler to produce the exact assembly code we want and still be flexible to support other vector engines in the future".<br/></div><br/>Ah. Ok. Thank you for the info.</div> text/html
    https://whatsonchain.com/tx/c4c173f62c5a7142d35c783722873a96b5ce8350bf0ba93356917b75bfd35a96