jmetaB039cd35a66ff1ce6a5f6976e8bb927ffd0b6bfaf8a462d35f091bf7d0a854ec4fe@4171e0b5905c0a612c8949b16d5afb553d735d24d7a7bba16a66254fce4ecd94rss.item metarss.netM6,<item> <title>Are You Ready For HBM4? A Silicon Lifecycle Management (SLM) Perspective</title> <link>https://semiengineering.com/are-you-ready-for-hbm4-a-silicon-lifecycle-management-slm-perspective/</link> <comments>https://semiengineering.com/are-you-ready-for-hbm4-a-silicon-lifecycle-management-slm-perspective/#respond</comments> <dc:creator><![CDATA[Faisal Goriawalla]]></dc:creator> <pubDate>Tue, 06 Aug 2024 07:05:21 +0000</pubDate> <category><![CDATA[Blogs - PTES]]></category> <category><![CDATA[Silicon Lifecycle Management]]></category> <category><![CDATA[Test, Measurement and Analytics]]></category> <category><![CDATA[BiST]]></category> <category><![CDATA[DRAM]]></category> <category><![CDATA[HBM]]></category> <category><![CDATA[high-bandwidth memory]]></category> <category><![CDATA[memory]]></category> <category><![CDATA[multi-die]]></category> <category><![CDATA[predictive maintenance]]></category> <category><![CDATA[silicon lifecycle management]]></category> <category><![CDATA[SLM]]></category> <category><![CDATA[Synopsys]]></category> <category><![CDATA[test]]></category> <guid isPermaLink="false">https://semiengineering.com/?p=24246825</guid> <description><![CDATA[<p>Detecting defects before system failure enables scheduled maintenance rather than unplanned downtime.</p> <p>The post <a href="https://semiengineering.com/are-you-ready-for-hbm4-a-silicon-lifecycle-management-slm-perspective/">Are You Ready For HBM4? A Silicon Lifecycle Management (SLM) Perspective</a> appeared first on <a href="https://semiengineering.com">Semiconductor Engineering</a>.</p> ]]></description> <content:encoded><![CDATA[<p>Many factors are driving system-on-chip (SoC) developers to adopt multi-die technology, in which multiple dies are stacked in a three-dimensional (3D) configuration. Multi-die systems may make power and thermal issues more complex, and they have required major innovations in electronic design automation (EDA) implementation and test tools. These challenges are more than offset by the advantages of over traditional 2D designs, including:</p> <ul> <li>Reducing overall area</li> <li>Achieving much higher pin densities</li> <li>Reusing existing proven dies</li> <li>Mixing heterogeneous die technologies</li> <li>Quickly creating derivative designs for new applications</li> </ul> <p>One of the most common uses of multi-die design is the interconnection of memory stacks and processors such as CPUs and GPUs. High Bandwidth Memory (HBM) is a standard interface specifically for 3D-stacked DRAM dies. It was defined by the <a href="https://www.jedec.org/">JEDEC Solid State Technology Association</a> in 2013, followed by HBM2 in 2016 and HBM3 in 2022. Many multi-die projects have used this standard for caches in advanced CPUs and other system-on-chip (SoC) designs used in high-end applications such as data centers, high-performance computing (HPC), and artificial intelligence (AI) processing.</p> <p><a href="https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig1.webp?ssl=1"><img decoding="async" class="alignnone size-full wp-image-24246826" src="https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig1.webp?resize=1430%2C519&ssl=1" alt="" width="1430" height="519" srcset="https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig1.webp?w=1430&ssl=1 1430w, https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig1.webp?resize=300%2C109&ssl=1 300w, https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig1.webp?resize=1024%2C372&ssl=1 1024w, https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig1.webp?resize=768%2C279&ssl=1 768w, https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig1.webp?resize=600%2C218&ssl=1 600w" sizes="(max-width: 1000px) 100vw, 1000px" data-recalc-dims="1" /></a></p> <p><strong>Fig. 1: Example of a current HBM-based SoC.</strong></p> <p>JEDEC recently <a href="https://www.jedec.org/news/pressreleases/jedec-approaches-finalization-hbm4-standard-eyes-future-innovations">announced</a> that it is nearing completion of HBM4 and published preliminary specifications. HBM4 has been developed to enhance data processing rates while maintaining higher bandwidth, lower power consumption, and increased capacity per die/stack. The initial agreement calls for speed bins up to 6.4 Gbps, although this will increase as memory vendors develop new chips and refine the technology. This speed will benefit applications that require efficient handling of large datasets and complex calculations.</p> <p>HBM4 is introducing a doubled channel count per stack over HBM3. The new version of the standard features a 2048-bit memory interface, as compared to 1024 bits in previous versions, as shown in figure 1. This intent is to double the number of bits without increasing the footprint of HBM memory stacks, thus doubling the interconnection density as well.</p> <p>Different memory configurations will require various interposers to accommodate the differing footprints. HBM4 will specify 24 Gb and 32 Gb layers, with options for supporting 4-high, 8-high, 12-high and 16-high TSV stacks. As an example configuration, a 16-high based on 32 Gb layers will offer a capacity of 64 GB, which means that a processor with four memory modules can support 256 GB of memory with a peak bandwidth of 6.56 TB/s using an 8,192-bit interface.</p> <p>The move from HBM3 to HBM4 will require further evolution in multi-die support across a wide range of EDA tools. The 2048-bit memory interface requires a significant increase in the number of through-silicon vias (TSVs) routed through a memory stack. This will mean shrinking the external bump pitch as the total number of micro bumps increases significantly. In addition, support for 16-high TSV stacks brings new complexity in wiring up an even larger number of DRAM dies without defects.</p> <p>Test challenges are likely to be a dominant part of the transition. Any signal integrity issues after assembly and multi-die packaging become more difficult to diagnose and debug since probing is not feasible. Further, some defects may marginally pass production/manufacturing test but subsequently fail in the field. Thus, test of the future HBM4-based subsystem needs to be accomplished not just at production test but also in-system to account for aging-related defects.</p> <p>Being able to monitor real-time data during mission mode operation in the field is greatly preferable to having to take the system offline for unplanned service. This âpredictive maintenanceâ allows the end user to be proactive rather than reactive. HBM provides capabilities for in-system repair, for example swapping out a bad lane. Even if a defect requires physical hardware repair, detecting it before system failure enables scheduled maintenance rather than unplanned downtime.</p> <p>As shown in figure 1, HBM systems typically have a base die that includes an HBM controller, a basic/fixed test engine provided by the DRAM vendor, and Direct Access (DA) ports. The new industry trend is for the base die to be manufactured on a standard logic process rather than the DRAM process. The SoC designer should include in the base die a flexible built-in self-test (BIST) engine that allows different algorithms to be used to trade off high coverage versus test time depending on the scenario.</p> <p>This engine must be programmable to handle different latencies, address ranges, and timing of test operations that vary across DRAM vendors. It may also need to support post-package repair (PPR) for HBM DRAM to delay any âtruck roll-outâ for in-field service. The diagnostics performed by the BIST engine must be precise, showing the failing bank, row address, column address, etc. if there is a defect detected in the DRAM stack. Figure 2 shows an example.</p> <p><a href="https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig2.webp?ssl=1"><img loading="lazy" decoding="async" class="alignnone size-full wp-image-24246827" src="https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig2.webp?resize=1066%2C756&ssl=1" alt="" width="1066" height="756" srcset="https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig2.webp?w=1066&ssl=1 1066w, https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig2.webp?resize=300%2C213&ssl=1 300w, https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig2.webp?resize=1024%2C726&ssl=1 1024w, https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig2.webp?resize=768%2C545&ssl=1 768w, https://i0.wp.com/semiengineering.com/wp-content/uploads/Synopsys_Ready-for-HBM4-SLM-Perspective-fig2.webp?resize=600%2C426&ssl=1 600w" sizes="(max-width: 1000px) 100vw, 1000px" data-recalc-dims="1" /></a></p> <p><strong>Fig. 2: Example fault diagnosis for HBM stack.</strong></p> <p>As an industry leader in multi-die EDA and IP solutions, Synopsys provides all the technology needed for HBM manufacturing yield optimization and in-field silicon health monitoring. Signal Integrity Monitors (SIMs) are embedded in physical layer (PHY) IP blocks for on-demand signal quality measurement for interconnects. This allows users to create 1D eye diagrams for interconnect signals during both production test and in-field operation. SIMs measure timing margins, enable HBM lane test/repair, and mitigate against silent data corruption (SDC), part of an effective silicon lifecycle management (SLM) solution.</p> <p>Synopsys SMS ext-RAM is a programmable and synthesizable engine that performs test, repair, and diagnostics for memory systems, including HBM. SMS ext-RAM ensures high test coverage and supports power-on self-test (POST) with the flexibility to run custom memory algorithms in-field. As shown in figure 2, it detects a wide range of defects in memory dies, including stuck-at faults, read destructive faults, write destructive faults, deceptive read destructive faults, and row hammering.</p> <p>A real world <a href="https://www.synopsys.com/content/dam/synopsys/solutions/slm/success-stories/socionext-and-synopsys-ss.pdf">case study</a> of a project using HBM with the Synopsys solutions is available. These solutions are scaling to support the emerging HBM4 standard, ensuring continued success.</p> <p>The post <a href="https://semiengineering.com/are-you-ready-for-hbm4-a-silicon-lifecycle-management-slm-perspective/">Are You Ready For HBM4? A Silicon Lifecycle Management (SLM) Perspective</a> appeared first on <a href="https://semiengineering.com">Semiconductor Engineering</a>.</p> ]]></content:encoded> <wfw:commentRss>https://semiengineering.com/are-you-ready-for-hbm4-a-silicon-lifecycle-management-slm-perspective/feed/</wfw:commentRss> <slash:comments>0</slash:comments> <post-id xmlns="com-wordpress:feed-additions:1">24246825</post-id> </item>
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