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jmetaB02224ab55f0aa7de31e6b1c49b12cfe6155189c4952075023ca4242d0240534d6b@4171e0b5905c0a612c8949b16d5afb553d735d24d7a7bba16a66254fce4ecd94rss.itemmetarss.netM0<item> <title>Sidestepping Lithography In Chip Manufacturing</title> <link>https://semiengineering.com/sidestepping-lithography-in-chip-manufacturing/</link> <comments>https://semiengineering.com/sidestepping-lithography-in-chip-manufacturing/#respond</comments> <dc:creator><![CDATA[Katherine Derbyshire]]></dc:creator> <pubDate>Thu, 23 May 2024 07:01:57 +0000</pubDate> <category><![CDATA[Manufacturing, Packaging and Materials]]></category> <category><![CDATA[Top Stories]]></category> <category><![CDATA[ALD]]></category> <category><![CDATA[area-selective ALD]]></category> <category><![CDATA[area-selective deposition]]></category> <category><![CDATA[Argonne National Laboratory]]></category> <category><![CDATA[atomic-level deposition]]></category> <category><![CDATA[edge placement error]]></category> <category><![CDATA[Hanyang University]]></category> <category><![CDATA[imec]]></category> <category><![CDATA[lithography]]></category> <category><![CDATA[ruthenium]]></category> <category><![CDATA[SAMs]]></category> <category><![CDATA[self-assembled monolayers]]></category> <category><![CDATA[Stanford Unviersity]]></category> <category><![CDATA[Université Grenoble Alpes]]></category> <guid isPermaLink="false">https://semiengineering.com/?p=24243911</guid> <description><![CDATA[<p>Selective deposition could slow the need for additional lithography steps, helping to control costs for advanced-node chips.</p> <p>The post <a href="https://semiengineering.com/sidestepping-lithography-in-chip-manufacturing/">Sidestepping Lithography In Chip Manufacturing</a> appeared first on <a href="https://semiengineering.com">Semiconductor Engineering</a>.</p> ]]></description> <content:encoded><![CDATA[<p>Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of <a href="https://semiengineering.com/knowledge_centers/manufacturing/process/deposition/atomic-layer-deposition/">atomic layer deposition</a>, ASD seeks to build circuit features from the bottom up, without relying on lithography.</p> <p>Lithography will remain a critical tool for the foreseeable future. But it has long been the most expensive process in semiconductor manufacturing, and it is becoming more so with the advent of EUV. Within a few device generations, even EUV tools will need multiple exposures to achieve the required feature sizes. <a href="https://semiengineering.com/managing-yield-with-euv-lithography-and-stochastics/">Edge placement error</a> is consuming a larger and larger share of the total error budget. Aligning new layers to existing features can eliminate lithography steps and reduce the impact of edge placement error.</p> <p>Shrinking feature sizes also are driving interest in ruthenium interconnects, potentially the biggest change to the interconnect stack since the introduction of copper. At line widths below 100nm, the resistivity of copper starts to increase due to interface scattering and other metals may give better performance. Ruthenium, unlike copper, diffuses relatively slowly and therefore does not need a barrier layer. As a result, the actual dimensions of a ruthenium line are larger than a copper line based on the same design rule.</p> <p>Meanwhile, the same trends that make lithography more difficult are making atomic layer deposition <a href="https://semiengineering.com/enabling-advanced-devices-with-atomic-layer-processes/">more cost-effective</a>. Thinner layers make the low deposition rate of ALD less of a concern.</p> <p><strong>Ruthenium where you want it, not where you don’t</strong><br /> Area-selective deposition is an umbrella term incorporating several different process schemes, including templated growth and topographic selectivity. Most recent research has been focusing on processes that derive selectivity from a pre-existing device pattern. For example, Jeong-Min Lee and Woo-Hee Kim at South Korea&#8217;s Hanyang University found that their Ru(TMM)(Co)₃ precursor has a high nucleation rate on silicon dioxide, but a low nucleation rate on titanium nitride.[⁠1] Ruthenium structures can therefore self-align themselves to fill oxide trenches.</p> <p>However, this intrinsic surface selectivity is not enough. As the deposition proceeds, material still accumulates on the non-growth surface. Once it is covered, selectivity is lost. The key challenge for ASD is to identify processes that are selective enough and to maintain sufficient selectivity until the desired film thickness is deposited.</p> <p>To phrase the problem a little more precisely, selectivity is defined as:</p> <p><img loading="lazy" decoding="async" class="alignnone wp-image-24243912" src="https://i0.wp.com/semiengineering.com/wp-content/uploads/formula.jpg?resize=177%2C67&#038;ssl=1" alt="" width="177" height="67" srcset="https://i0.wp.com/semiengineering.com/wp-content/uploads/formula.jpg?w=454&amp;ssl=1 454w, https://i0.wp.com/semiengineering.com/wp-content/uploads/formula.jpg?resize=300%2C114&amp;ssl=1 300w" sizes="(max-width: 177px) 100vw, 177px" data-recalc-dims="1" /></p> <p>G_g and G_ng are growth rates on the desired and undesired areas, respectively. Additional surface treatments can be used to encourage deposition in the growth areas, discourage it in the non-growth areas, or both.</p> <p>One of the simplest ASD approaches depends on self-assembled monolayers to create a physical barrier to the precursor gases. Self-assembled monolayers (SAMs) use monomers with a functional group attached to one end. The functional group is designed to adhere to the non-growth region.</p> <p>SAMs are very versatile. They can be designed to adhere to almost any surface, but they are difficult to incorporate into semiconductor manufacturing. They usually are applied by immersing the wafer in a monomer solution, then allowing time for the deposited molecules to arrange themselves. The procedure takes anywhere from several hours to a full day. Even then, pinholes and other defects in the coating are common. While vapor-phase SAMs do exist [^â2], both vapor-phase and solution-based molecules are inherently fairly large, typically 2 to 3nm. Insinuating them into small trenches with room left over for the deposited film becomes more difficult as feature sizes shrink.</p> <p>The limitations of SAMs are helping to motivate research into small molecule inhibitors. These typically work by chemically passivating the non-growth surface. However, as Stacey Bent, professor of chemical engineering at Stanford University, pointed out in a presentation at this year’s Materials Research Society (MRS) Spring Meeting, the shape and orientation of inhibitor molecules still matters. For instance, pyridine is not a very good inhibitor for ruthenium deposition, while other nitrogenous aromatics like pyrole and aniline are very effective. From DFT calculations, Bent said, pyridine appears to bind to the surface in an upright position, while the other two are planar. Reactions and miscibility between the inhibitor and the precursor also play a role. For instance, Bent said, methanesulfonic acid is a good inhibitor for aluminum deposition from DMAI (dimethylaluminum isopropoxide) on copper, but not for other metals or other precursors.[^â3]</p> <p>The blocking capacity of an inhibitor depends on the degree to which the inhibitor is able to coat the surface, too. The Hanyang University work, mentioned above, used (N,N-diethylamino) trimethylsilane (DEATMS) as an inhibitor for ruthenium deposition. The researchers found that DEATMS molecules chemisorbed on each other, screening the underlying surface. Using a “cut-in purge” step to flush excess DEATMS and re-expose the surface resulted in more complete passivation.</p> <p>Imec senior researcher Annelies Delabie said in an interview that one of the highlights of a recent <a href="https://www.asd2024.ca">ASD workshop</a> was the number of systematic studies of the interactions between potential precursors and potential inhibitor chemicals. Delabie emphasized that precursors, inhibitors, and the process conditions all must work together to achieve the desired results. The degree to which a precursor reacts with or even removes an inhibitor molecule determines the selectivity, the growth rate, and how often the inhibitor will need to be replenished.</p> <p>For instance, Angel Yanguas-Gil, principal materials scientist at Argonne National Laboratory, noted in an MRS presentation that the removal rate of excess precursor gas is usually lower than the purge gas flow rate.[⁠4] The precursor’s interaction with the surface imposes resistance to the gas flow. Incomplete purging between ALD steps can lead to cross-contamination and defects. He pointed out that, beyond applications in semiconductor manufacturing, ASD is an excellent model system for fundamental studies of surface reactivity. Lessons learned here can also apply to sensors and catalysts, among others.</p> <p><strong>Etching for better selectivity, more process parameters</strong><br /> Many process schemes also depend on selective etching to clear material from non-growth areas, either instead of, or in addition to, the use of inhibitors. In a comprehensive review, Marceline Bonvalot, associate professor at Université Grenoble Alpes, and her colleagues detailed some of the requirements the etch step in such a scheme must meet. The first priority, of course, is high selectivity to both the growth areas and the underlying substrate material, combined with passivation of non-growth surfaces. Etching should not damage the desired film in growth areas, either by introducing contaminants or by degrading density or roughness. Process engineers also need to remember that introducing etch chemistry into a deposition chamber poses a risk of cross-contamination due to reactions between the etch chemistry and the chamber’s walls.[^â5]</p> <p><strong>Slow</strong><strong>, but still useful</strong><br /> Complex super cycles with inhibitor deposition and selective etch steps naturally incur a throughput penalty. If ALD is slow, ASD is even slower. Typically, selective deposition takes two or three times as long as ALD for an equivalent final thickness. It’s worth it, though, if it allows the fab to reduce the number of lithography steps.</p> <p><strong>References</strong></p> <ol> <li>J. -M. Lee and W. -H. Kim, &#8220;Area-Selective Atomic Layer Deposition of Ruthenium Thin Films by Chemo-Selective Adsorption of Short Alkylating Agents,&#8221; 2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM), Dresden, Germany, 2023, pp. 1-3, doi: 10.1109/IITC/MAM57687.2023.10154801.</li> <li>H. Park, et al., &#8220;Area-Selective Atomic Layer Deposition of Ruthenium Thin Films Using Aldehyde Inhibitors,&#8221; 2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM), Dresden, Germany, 2023, pp. 1-3, doi: 10.1109/IITC/MAM57687.2023.10154817.</li> <li>Stacey F. Bent, “Controlling Interfaces toward Area Selective Atomic Layer Deposition,” Materials Research Society Spring Meeting, Seattle, 2024. Paper EL01.01.01.</li> <li>Angel Yanguas-Gil, “Scaling and Scale Up Effects during Area Selective Deposition using Self-Assembled Monolayers and Small Molecule Inhibitors,” Materials Research Society Spring Meeting, Seattle, 2024. Paper EL01.02.05.</li> <li>Marceline Bonvalot, et al., “Area selective deposition using alternate deposition and etch super-cycle strategies,” Dalton Trans., 2022,51, 442-450. https://doi.org/10.1039/D1DT03456A</li> </ol> <p>The post <a href="https://semiengineering.com/sidestepping-lithography-in-chip-manufacturing/">Sidestepping Lithography In Chip Manufacturing</a> appeared first on <a href="https://semiengineering.com">Semiconductor Engineering</a>.</p> ]]></content:encoded> <wfw:commentRss>https://semiengineering.com/sidestepping-lithography-in-chip-manufacturing/feed/</wfw:commentRss> <slash:comments>0</slash:comments> <post-id xmlns="com-wordpress:feed-additions:1">24243911</post-id> </item>